curriculum vitae

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Summary:

Education:

Work Experience

Organization Designation Duration
Freescale Semiconductors (FSL) Noida, India Applications Engineering Manager 2010 – 2012
Freescale Semiconductors (FSL) Noida, India Applications Engineer 2009 – 2010
Freescale Semiconductor (FSL) Noida, India Design Manager 2006 – 2009
Freescale Semiconductor (FSL) Noida, India IC Design Engineer II 2005 – 2006
Texas Instruments (TI) Bangalore, India Lead Engineer 2004 – 2005
Interra Systems India Pvt. Ltd, Noida, India Senior Design Engineer 2003 – 2004
Cogency Semiconductor Inc., Toronto, Canada ASIC Design Engineer 2001 – 2003
Tundra Semiconductors, Ottawa, Canada Emulation Engineer 2001 – 2001
STMicroelectronics (STM) Noida, India Team Leader 1999 – 2001
STMicroelectronics (STM) Noida, India Design Engineer 1998 – 1999

Technical summary:

Hardware Design: HDL based design and verification, targeting both ASICs and FPGAa.

HDL Exposure: Verilog, VHDL, SystemVerilog, Bluespec SystemVerilog

Embedded Systems Design: Have developed and debugged hardware and software

Prototyping: Experience in prototyping complex designs using FPGAs.

Emulation: Emulation of complex digital designs on Quickturn’s Mercury™ emulation platform.

Scripting languages: perl, gawk, bash, tcsh and tcl/tk

Selected Accomplishments:

Design Related:

Methodologies related:

Published Work

  1. M. Ajmal, A. Samad, and M.H. Minai, “Basics of FPGA design in context with AES algorithm,” proceedings of national conference on Emerging Technologies NCET-08 Lucknow, pp. 313-318, March 29th – 30th, 2008.

  2. Kafeel M.A and Minai H.,”FPGA based AES Hardware implementation for secure management of systems”, proceedings of the All India seminar on communication convergence, institution of engineers, Lucknow, India, September 8th - 9th, 2007.

Mentoring Activities

Contact Details